JFET Biasing Worked Out Example Calculation

 In this tutorial we illustrate how to bias JFET transistor with worked out example calculation. This is follow up tutorial for previous tutorial how to bias JFET transistor. The JFET transistor used is 2N5459 N channel JFET. The worked out example starts with fundamental and basic gate shorted JFET circuit. Then resistor are added to gate shorted JFET circuit. The calculation are shown along with the circuit. Then self bias circuit and voltage divider biased JFET circuit is explained with worked out calculation for calculating the resistor values and voltages to bias the circuit.

Gate Shorted

 Consider the case when the gate of the JFET is shorted(grounded), that is \(V_{GS}\)=0. Let use \(V_{DD}\)=+5V between the drain and source. In this case, maximum current \(I_{DSS}\) flows through the transistor from drain to source. The transistor is completely ON. The circuit is shown below.

circuit diagram of gate shorted JFET

To find the drain to source resistance we can use the following approximate formula,

\(R_{DS} = \frac{V_P}{I_{DSS}}\)    ------------->(1)

The values of \(V_P\) and \(I_{DSS}\) are obtained either from the datasheet or drain curve graph or physically measured. Often we want to perform simulation and test the desired circuit design before actually building the circuit to save time. When electronics design software is used to test the circuit we rely on spice model accuracy of the JFET component. Here we will be using Proteus Software and the spice model used by the software.

 In Proteus we can plot the drain characteristics of the 2N5459 JFET which is shown below.

drain characteristics of 2N5459 JFET in Proteus

 To know how to plot drain curve in proteus see the tutorial Import spice model in Proteus and draw JFET drain curve.

The top curve is for \(V_{GS}\)=0. From the graph we can see that \(I_{DSS}\) = 10mA and \(V_P\)=1.2V. Thus from eqn(1) above,

\(R_{DS} = \frac{V_P}{I_{DSS}} = \frac{1.2V}{10mA}=120\Omega\) 

Next consider the circuit when drain resistor \(R_D\) is added in the circuit. 

circuit diagram of gate shorted JFET with drain resistor

The equation for the drain voltage and drain resistor can be derived as following equation,

\(V_{DD}=V_D+I_D R_D\)  -------------->(2)

which gives drain voltage, 

\(V_D=V_{DD}-I_D R_D\) ----------------->(3)

and also drain resistor,  

\(R_D=\frac{V_{DD}-V_D}{I_D}\)  ------------->(4)

Suppose we want the voltage at the drain \(V_D\) to be 2.5V, then we can calculate the required value for the drain resistor from eqn.(4) as follows,

\(R_D=\frac{5V-2.5V}{10mA} = 250\Omega\) 

The circuit diagram with \(R_D=250\Omega\) is shown below.

circuit diagram of gate shorted JFET with drain resistor

The measured drain voltage and drain current for the above circuit is shown below.

simulated circuit diagram of gate shorted JFET with drain resistor


Applying Fixed Gate Bias

Next we consider what happens when a fixed bias or gate bias is added to the circuit. The gate bias is connected such that the gate to source voltage\(V_{GS}\) is reversed biased. As the reverse gate bias is increased(more negative) the drain current decreases. Let us apply fixed gate bias of \(V_{GS}\)=600mV which is half of the \(V_P\)=1.2V from the above drain curve. The fixed gate bias circuit is as shown in the figure.

circuit diagram of fixed gate bias JFET

The drain current \(I_D\) is controlled by the the gate to source voltage\(V_{GS}\) and is dictated by the Shockley equation as follows,

\(I_D = I_{DSS}(1- \frac{V_{GS}}{V_P})^2\)  --------------->(5)

Once we know the drain current \(I_D\), we can set the drain voltage \(V_D\) using the resistor \(R_D\) using the equation (4) above.

However, using the above Shockley equation, it turns out that the calculated value for drain current \(I_D\) does not result into expected value for drain voltage. For example, we have used in above calculation  \(I_{DSS}\) = 10mA and \(V_P\)=1.2V from the drain curve characteristic(obtained from the spice model of 2N5459 JFET). Using these values along with \(V_{GS}\)=0.6V in Shockley equation gives drain current \(I_D\) = 2.5mA. Suppose we want the drain voltage \(V_D\) =2.5V. To get \(V_D\) =2.5V we can use the eqn(4) above and with \(I_D\) = 2.5mA and \(V_{DD}\) =5V we get \(R_D=1K\Omega\). Using \(V_{GS}\)=0.6V and \(R_D=1K\Omega\) in the circuit then should give \(V_D\) =2.5V but the voltage is 3.4V as shown in the following picture.

simulated circuit diagram of fixed gate bias JFET

So what is the correct way to calculate drain current \(I_D\)? It turns out that we have to refer to the drain characteristics curve instead. The drain curve characteristics depends upon the spice model for the JFET used in the circuit simulation software which in this case is Proteus.

From the drain curve characteristics we have to look for drain current \(I_D\) when \(V_{GS}\)=0.6V and when \(V_{DS}\) =2.5V. The following shows drain current \(I_D\)=1.6mA when \(V_{GS}\)=0.6V and when \(V_{DS}\) =2.5V.

 Using \(I_D\)=1.6mA obtained from the graph in eqn(4) we can obtain the drain resistor value as follows,


With \(R_D=1.56K\Omega\), the drain voltage \(V_D\) is 2.5V as illustrated in the circuit simulated diagram below.

simulated circuit diagram of fixed gate bias JFET

Often for ac operation we add a gate resistor as shown below. This added gate resistor will not effect the reverse biasing of the gate to source voltage.

circuit diagram of fixed gate bias JFET with gate resistor

In this way we can apply fixed gate bias to operate JFET transistor in the ohmic region.

JFET Self Bias

Now we consider self biasing of JFET. Self biasing is a method wherein a resistor \(R_S\) is added to the source terminal. The following is circuit diagram of a self bias JFET circuit.


circuit diagram of self bias JFET with gate resistor

This source resistor \(R_S\) is used to apply a negative gate to source voltage \(V_{GS}\) which is needed to operate a JFET. By using a source resistor voltage is developed across it which provides feedback to the gate and thus a separate power supply is not required in this circuit configuration. Because of this it is called self bias. Self bias also stabilizes the operating condition, that is the drain current is stabilized to certain extent. When the drain current increases, the source voltage across the source resistor is increased and thereby the gate to source voltage is increased. This increase in gate to source voltage decreases the drain current.

In self bias, the voltage at the source \(V_S\) is equal to the gate to source voltage \(V_{GS}\).

 \(V_S\) = -\(V_{GS}\)   ----------------->(6)

The drain current flows through the source resistor \(R_S\) so the source voltage \(V_S\) is,

 \(V_S\) = \(I_{D} R_{S}\)   ----------------->(7)

Therefore combining (6) and (7) we have,

 \(V_{GS}\) = - \(I_{D} R_{S}\)   -------------->(8)

In self biasing of JFET, the operating point or the quiescent point Q, is selected such that drain current \(I_{D}\) has maximum swing possible between 0 and \(I_{DSS}\). One way to find such Q point is to select \(V_{GS}\) midway between 0 and \(V_{GS(off)}\). This is diagrammatically shown below.

From equation (7) above we can see that the source resistor \(R_S\) controls the gate to source voltage \(V_{GS}\) which is the reverse bias voltage to control the drain current in JFET. It is found that when the source resistor \(R_S\) is approximately equal to the JFET drain to source resistance \(R_{DS}\) then \(V_{GS}\)=\(\frac{V_{GS(off)}}{2}\). Also when \(V_{GS}\)=\(\frac{V_{GS(off)}}{2}\) then the drain current is one forth of \(I_{DSS}\), that is, \(I_{D}\)=\(\frac{I_{DSS}}{4}\). This is due to the Shockley equation (5) above and illustrated diagrammatically below.

So using this idea of midpoint bias we have,

\(V_{GS}=\frac{V_{GS(off)}}{2}\)    ------------>(9)

Since \(V_{GS(off)}=V_P=1.2V\) from the drain curve characteristics above, we have from eqn(9),



Now at this point we should be using the fact that the drain current \(I_D\) should be one fourth of \(I_{DSS}\), that is 

\(I_D = \frac{I_{DSS}}{4}\)  ------------------>(10)

which gives, \(I_D = \frac{10mA}{4}=2.5mA\) but this obtained value \(I_D = 2.5mA\) will not give expected result when the circuit is simulated.

Instead what we have to do is to use the drain current \(I_D\) from the drain curve for \(V_{GS}=0.6V\). From the drain curve as before, \(I_D = 1.6mA\). With this value of drain current the simulated circuit will give expected result as will be illustrated next.

With drain current \(I_D = 1.6mA\) and using equation (8) we can calculate the source resistor value as follows,

  \(V_P(=V_{GS})\) = \(I_{D} R_{S}\) 

that is, \(R_S=\frac{V_{GS}}{I_D}=\frac{0.6V}{1.6mA}=375\Omega\) 

Next step is to calculate the drain resistor value. We can calculate the drain resistor value using the equation (4) above. Let us choose drain voltage \(V_D\)=2.5V then,

\(R_D=\frac{V_{DD}-V_D}{I_D} = \frac{5V-2.5V}{1.6mA}=1.56K \Omega\)

The self bias circuit diagram with the calculated resistor values is shown below.

calculated circuit diagram of self bias JFET with gate resistor

 The following shows simulated circuit with drain voltage, gate to source voltage and the voltage at the source.

simulated circuit diagram of self bias JFET with gate resistor

 So in this we can bias a JFET transistor using self bias. For example of circuits that uses self bias see Self Biased JFET Colpitts Oscillator and Headphone Amplifier using JFET.

Voltage Divider Bias

 Next we consider how to bias JFET transistor using voltage divider biasing method. The circuit diagram of biasing JFET using voltage divider biasing method is shown below.

simulated circuit diagram of voltage divider bias JFET

For operating the JFET transistor in active region, the quiescent point Q or the operating point should be in the middle of the transfer characteristic curve so that maximum swing for input gate to source voltage \(V_{GS}\) and output drain current \(I_D\) can be achieved. For this reason we set the gate to source voltage \(V_{GS}\) half of the \(V_{GS(off)}\) or the pinch off voltage \(V_P\) of the JFET transistor. This is illustrated below.

 The gate voltage \(V_G\) is provided by the voltage divider circuit formed by the resistor R1 and R2. The gate voltage is determined by the following voltage divider equation.

\(V_G=(\frac{R_2}{R_1+R_2})V_{DD}\)   ---------------->(11)

  This gate voltage \(V_G\) is used to set the gate to source voltage \(V_{GS}\) in reverse biased condition. So if \(V_G\) = |\(V_{GS}\)| then the gate to source voltage is reversed biased. Therefore the gate voltage is for mid-point operating point is,

\(V_G\) = \(|V_{GS}| = \frac{V_{GS}}{2}=\frac{1.2V}{2}=0.6V\)

Using equation(11) we can then calculate the resistor values. Rearranging equation(11) for solving resistor R1 provided arbitrary chosen value for resistor R2,

\(R_1=(\frac{V_{DD}-V_G}{V_G}) R_2\)

Let \(R_2=1k\Omega\), then

\(R_1=(\frac{5V-0.6V}{0.6}) 1k\Omega \)

therefore, \(R_1=7.33 k\Omega \)

Now the gate to source voltage \(V_{GS}\) is,


Therefore the source voltage \(V_S\) is,


or,   \(V_S=0.6V-(-0.6V)=1.2V\)

From the drain curve we have for \(V_{GS(off)}\)=-0.6V we have the drain current of \(I_D\)=1.6mA. This was explained in the gate bias and self bias methods above.

The source voltage \(V_S\) across the source resistor \(R_S\) is,

\(V_S=I_D R_S\)

Therefore,  \(R_S = \frac{V_S}{I_D}=\frac{1.2V}{1.6mA}=750\Omega\)

Finally we calculate the drain resistor \(R_D\). For this we need to set the desired drain voltage  \(V_D\). Let the drain voltage \(V_D\) =2.5V, then we have,

\(V_{DD}=V_D+I_D R_D\)

rearranging for drain resistor,

\(R_D = \frac{V_{DD}-V_D}{I_D}\)

or, \(R_D = \frac{5V-2.5V}{1.6mA}\)

that is,  \(R_D = 1.56k\Omega\)

Hence the voltage divider biased JFET circuit with the calculated value is shown below.

calculated simulated circuit diagram of voltage divider bias JFET
 The following shows the simulated current and voltages for the above circuit,

simulated circuit diagram of voltage divider bias JFET

So in this tutorial we showed how to calculate resistors and voltages for biasing JFET transistor. Learning how to bias a JET transistor is helpful because then one can design application circuit using JFET. Following are some example of usage of JFET transistor.

- AM modulator using JFET transistor 

- AM modulator design with Two JFET transistors.


Post a Comment

Previous Post Next Post