How to design JFET source follower?

Here it is illustrated how to design a JFET source follower with worked out example using 2N5459 JFET transistor. The source follower JFET circuit is also called common drain JFET in which the drain is common to both the input and the output. The input is applied to the drain and the output is taken from the source. 

The following shows the circuit diagram of JFET source follower.

common drain JFET circuit diagram

The above source follower circuit is biased using voltage divider biasing method. The capacitors Cc1 and Cc2 are coupling capacitors. RL is the load resistor where the output signal appears. The input impedance is very high in case of source follower and the output impedance is very low.

The process of designing JFET source follower circuit is as follows.

1. Determine the Q-point for the circuit(find \(V_{GS}\) and \(I_D\)

2. Bias the gate for desired \(V_{GS}\) 

3. Determine the source resistor \(R_S\)

4. Determine the drain resistor \(R_D\)

5. Determine the coupling capacitors \(C_{c1}\) and \(C_{c2}\)


 1. Determine the Q-point for the circuit(find \(V_{GS}\) and \(I_D\)

 Here first we set gate to source voltage \(V_{GS}\) and then find drain current \(I_D\) using either Shockley equation or use graphically method. It is best to use \(V_{GS}\) in the midpoint between the pinch off voltage \(V_P=-V_{GS(off)}\) and 0V. This is because this will give maximum swing for the output drain current \(I_D\) as illustrated graphically below.

The above graph shows the location of the Q-point or the operating point.

For 2N5459 JFET transistor in this tutorial the pinch off voltage \(V_P\) is 1.2V. Hence the gate to source voltage \(V_{GS}\) is,


The drain current \(I_D\) when \(V_{GS}=-0.6V\) can be determined either using Shockley equation or from the drain graph. Here the drain graph is plotted for the 2N5459 JFET model in Proteus Software and the value of \(I_D\) for \(V_{GS}=-0.6V\) is used in the calculations. The drain graph of 2N5459 in proteus software is shown below.

drain curve for JFET in proteus 

How to plot drain curve or transfer curve was explained in the tutorial Import spice model in Proteus and draw JFET drain curve

From the drain graph when \(V_{GS}=-0.6V\) the drain current is,



2. Bias the gate for desired \(V_{GS}\) 

The next step is to bias the gate with gate to source voltage, that is,

\(V_G = V_{GS} = 0.6V\) 

To get  \(V_G = 0.6V\) we will calculate the voltage divider biasing resistor \(R_1\) and \(R_2\) values. The gate voltage due to voltage divider circuit is,

\(V_G = (\frac{R_2}{R_1+R_2}) V_{DD}\) 

And selecting \(R_2=1k\Omega\), we have,

\(R_1=(\frac{5V-0.6V}{0.6}) 1k\Omega \)

therefore, \(R_1=7.33 k\Omega \)

 Now with this gate voltage reverse biases the gate to source voltage.


3. Determine the source resistor \(R_S\)

The value of the source resistor \(R_S\) can be determined using the following equation,


or, \(V_S=V_G-V_{GS}\)

or,  \(V_S=0.6V-(-0.6V)=1.2V\)

that is,  \(R_S = \frac{V_S}{I_D}=\frac{1.2V}{1.6mA}=750\Omega\)


4. Determine the drain resistor \(R_D\)

The value of the drain resistor \(R_D\) can be determined using the following equation,

 \(V_{DD} = I_D R_D - V_D\)

or, \(R_D = \frac{V_{DD}-V_D}{I_D}\)

Let us set the drain voltage \(V_D = 2.5V\), then

\(R_D = \frac{5V-2.5V}{1.6mA}\)

that is,  \(R_D = 1.56k\Omega\)


5. Determine the coupling capacitors \(C_{c1}\) and \(C_{c2}\)

Assume that the frequency of the input signal to the JFET source follower is 1KHz. 

To calculate the input coupling capacitor \(C_{c1}\) we need to find out the input impedance \(Z_{in}\). The input impedance is,

\(Z_{in}= R_1 || R_2\)

which results into,

\(Z_{in} = 7.33 k\Omega || 1 k\Omega = 880 \Omega\)

And the input coupling capacitor \(C_{c1}\) is,

\(C_{c1}=\frac{1}{2 \pi (f) (0.1) (Z_{in})}\)

The formula for coupling capacitor is explained in the tutorial How to bias a BJT using voltage divider biasing.

 \(C_{c1}=\frac{1}{2 \pi (1kHz) (0.1) (880 \Omega)} = 1.8 \mu F\)

Similarly the output coupling capacitor is calculated using the formula,

 \(C_{c2}=\frac{1}{2 \pi (f) (0.1) (Z_{out})}\)

where the output impedance is,

 \(Z_{out}= R_S || \frac{1}{g_m}\)

From the datasheet of 2N5459 JFET, the transconductance \(g_m\) varies from 2000uS to 6000uS. Taking the average value of 4000uS for transconductance \(g_m\) we have,

 \(Z_{out}= R_S || \frac{1}{4000 \mu S}\)

or,  \(Z_{out}= 750 \Omega || 250 \Omega\)

that is, \(Z_{out}= 187.5 \Omega\)

Hence, the output coupling capacitor is,

 \(C_{c2}=\frac{1}{2 \pi (1 kHz) (0.1) (187.5\Omega)}\)

that is,   \(C_{c2}=8.49 \mu F\)


Simulation and Results

The completed circuit diagram of common drain JFET with the calculated resistor and capacitor is shown below.

source follower JFET circuit diagram

The following shows simulated voltages in the circuit.


If we apply an input signal of 100mV amplitude and frequency of 1KHz then the input and output waveform is as shown in the oscilloscope below.

In the above oscilloscope graph, the yellow trace is the input signal and the blue trace is the output signal. As can be observed, the amplitude of the output signal waveform is lower than that of the input signal waveform. This illustrates the nature of JFET common drain amplifier or source follower. The voltage gain of source follower is less than unity or one. But the advantage of JFET source follower is that the input impedance is high and output impedance is low.

So here we explained how common drain configuration or source follow JET works with example calculation. Other configuration are possible and explained in common source JFET and common gate JFET

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