How to design JFET Reactance Modulator

Reactance modulator are RF modulators that changes the reactance of a transistor in accordance with the input modulating signal. Such reactance modulator when connected to oscillator circuit such as Hartley oscillator or Colpitts oscillator or Pierce oscillator, the modulating signal can change the frequency of the oscillator and thus generate FM signal. Hence reactance modulator are mostly used in the production of FM signal. This frequency modulation method using reactance modulator is often called direct method of FM generation. Thus reactance modulator are used in FM transmitter. Reactance modulator can be build with JFET or bipolar junction transistors(BJT). Here the theory behind the working principle of JFET based reactance modulator is explained and the required equation is given.

A JFET is a voltage controlled current output device. The gate when grounded gives the maximum drain current called gate shorted drain saturated current. So JFET are called normally ON device. In order to decrease the current we apply negative gate voltage to the JFET. The relation between the input gate voltage and the output current is through the transconductance gm. The graph of drain current vs the gate to source voltage is known as the transconductance curve. 

The transconductance of a JFET is defined as,

\(g_m = \frac{i_d}{v_{gs}}\)

The transconductance \(g_m\) is the ratio of ac drain current and ac gate to source voltage.

The transconductance curve equation is,

\( I_D = I_{DSS}(1-\frac{V_{GS}}{V_{GS(off)}})^2 \)

The transconductance, \(g_m\), can also be written as,

\( g_m = g_{m0}(1-\frac{V_{GS}}{V_{GS(off)}}) \)

where, \(g_{m0} = \frac{-2I_{DSS}}{V_{GS(off)}}\) is the maximum value of transconductance which occurs when gate to source voltage is zero, that is when \(V_{GS}=0\)

The following shows the basic circuit of a JFET transistor as a reactance device which forms main part of a reactance modulator.

jfet reactance circuit diagram

In this circuit a capacitor C1 and resistor R1 are connected as voltage divider network at the gate of the JFET. This JFET as a whole will effectively behave as a capacitive reactance device when certain condition are met. 

In case of JFET the gate current is very very small compared to the drain current, so the current i from the source goes through resistor R1 because gate current ig is negligible. This is the first condition for the JFET to behave as a reactance device.

For this the JFET impedance Z should be capacitive reactive.

We have,

\(Z = \frac{v}{i_d}\)

where v is the ac voltage at the drain and id is the ac drain current.

since, \(i_d = g_m v_{gs}\)

\(Z = \frac{v}{g_m v_{gs}}\)

The ac gate to source voltage is,

 \(v_{gs} = \frac{R_1v}{R1-jX_{C_1}}\)

where \(X_{C1}=\frac{1}{2\pi f C_1}\) is the capactive reactance of capacitor C1

Thus, \(Z = \frac{v}{g_m \frac{R_1v}{R1-jX_{C_1}}}\)

or, \(Z = \frac{R_1-jX_{C_1}}{g_mR_1}\)

or, \(Z = \frac{1}{g_m}(1-\frac{jX_{C_1}}{R_1})\)

if the capacitive reactance is much much greater than resistance R1, that is, if \(X_{C_1}>>R_1\),we will have,

or, \(Z = \frac{-jX_{C_1}}{g_m R_1}\)

which shows that if \(X_{C_1}>>R_1\), the impedance of the JFET is capacitive reactive. This is the second condition to be satisfied in order for the JFET to be used as capacitive reactance device.

We can rewrite the above equation as follows,

 \(Z = \frac{-jX_{C_1}}{g_m R_1} = -j X_{eq}\)

where,\(X_{eq} = \frac{X_{C_1}}{g_m R_1}=\frac{1}{2\pi f C_1 g_m R_1}=\frac{1}{2\pi f C_{eq}}\)

where, \(C_{eq}= g_m R_1 C_1 \)

which is the equivalent capacitance of the JFET.

That is,   \(Z =\frac{ -j}{2 \pi f C_{eq}}=\frac{1}{j w C_{eq}}\)

We had the condition that in order for the JFET impedance to be capacitive reactance, we require that the capacitive reactance of C1 be much larger than the resistance R1. In practice the the capacitive reactance is made 5 to 10 times larger than R1. Let n be the multiple of R1 equal to the capacitive reactance then we may write,

\(X_{C_1} = n R_1\)

Then the equivalent capacitance of the JFET is,

\(C_{eq}= g_m R_1 C_1 = g_m C_1 \frac{X_{C_1}}{n} = g_m C_1 \frac{1}{2 \pi f n C_1}=\frac{g_m}{2 \pi n f} \)

Thus, \(C_{eq}= \frac{g_m}{2 \pi n f} \)

As can be seen from the above equation, the equivalent capacitance of the JFET is controlled by the transconductance \(g_m\) which is in turn controlled by the basing modulating input voltage. This equation represents the main equation for designing JFET reactance device that is ultimately connected to oscillator to make a JFET reactance modulator. The values can be calculated using the online reactance modulator calculator.

Video demonstration of JFET Reactance Modulator

The following video shows how a JFET(Junction Field Effect Transistor) reactance modulator works.

Once you have build a JFET reactance device and connected to oscillator circuit such as Colpitts crystal oscillator, Hartley oscillator you can then use the above JFET reactance modulator design equation to calculate the equivalent capacitance need to be connected with the oscillators capacitor or inductor to for desired frequency of oscillation. You can utilize the oscillator frequency calculator in this design step. Then you need to calculate the value for the capacitor and resistor to bias the JFET transistor.


[1] FM modulation matlab code

[2] FM generation using VCO 

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