Phase Locked Loop at Receiver

 A Phase-Locked Loop (PLL) is commonly used in receiver circuits to recover and synchronize the incoming signal's phase and frequency. It is used for synchronous detection in AM receiver, FM demodulation, frequency multiplication, automatic frequency control of television amplifier, FSK(frequency shift keying) decoder etc. The PLL helps maintain a stable and accurate clock signal, which is crucial for extracting and decoding the transmitted information. Example of PLL IC are LM566 VCO IC

The following shows phase locked loop(PLL) used at the communication receiver.

Phase Locked Loop Circuit

In a receiver, the PLL typically consists of several key components:

  • Voltage-Controlled Oscillator (VCO): The VCO generates an output signal with a frequency that can be adjusted by an input voltage. Its frequency is typically set to be close to the expected frequency of the incoming signal.
  • Phase Detector/Comparator: The phase detector compares the phase of the incoming signal with the phase of the VCO output signal. It produces an output voltage that is proportional to the phase difference between the two signals. The phase detector is a dc coupled mixer with two ac signal input or two input XOR circuit.
  • Loop Filter: The loop filter is a low-pass filter that smooths and filters the output voltage from the phase detector. It removes any high-frequency noise or unwanted components from the phase difference signal.
  • Feedback Loop: The output of the VCF is fed back to the control input of the VCO, creating a closed loop. The VCO adjusts its frequency based on the filtered phase difference signal, attempting to minimize the phase difference and lock onto the incoming signal's frequency and phase.

phase locked loop circuit diagram The operation of the PLL involves a control mechanism that continuously adjusts the VCO frequency to match the incoming signal's frequency. Initially, when the receiver is turned on or there is no signal, the PLL may enter an acquisition phase where it attempts to lock onto the incoming signal. In this condition, there will be no error output voltage and the VCO will be running at its natural or free running frequency(\(f_0\).

If an input signal with frequency \(f_s\) is received, error voltage is generated at the output of the phase detector. The error voltage generated is proportional to the phase difference between the input signal and VCO signal. The output signal of the phase detector consist of signal which has sum and difference frequencies \(f_s+f_0\) and \(f_s-f_0\). The low pass filter blocks the sum frequency and allows to pass the difference frequency. The low pass filtered signal is the amplified and fed into the voltage controlled oscillator(VCO). The VCO output is such that it generates signal which has same phase as the input signal. 

Once locked onto the input signal phase, the PLL maintains synchronization by continuously tracking any variations in the incoming signal's phase and frequency. The VCO adjusts its frequency accordingly, ensuring that the local clock signal generated by the PLL remains in phase with the incoming signal.

By using a PLL at the receiver, it becomes possible to accurately recover the transmitted information and demodulate the signal, even in the presence of noise, frequency variations, or other distortions that may affect the received signal.


[1] Types of Frequency Demodulation Circuits

[2] How LM566/NE566 Voltage Controlled Oscillator(VCO) Works

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