JFET Hartley Oscillator

 If you want to design communication circuit or RF circuit in your project you might want to use an electronic oscillator. There are many types of oscillators. Some are based on op-amps some are based on transistors and so on. There are two things required for creating an oscillator. One is an amplifier and one is a feedback circuit. For amplifier you can use op-amp or transistors and for the feedback circuit there are RC filters, LC resonant tank etc. 

Here we look at how to design Harley oscillator using JFET(Junction Field Effect) transistor. The JFET will be used as an amplifier. The feedback circuit for the oscillator is LC resonant tank which is essentially a filter tuned to the desired oscillator frequency.

JFET Hartley Oscillator Circuit Diagram

 The following shows the Hartley oscillator circuit diagram.

JFET hartley oscillator circuit diagram
 The above Hartley oscillator has two major components- an amplifier and feedback circuit. These are explained next.

JFET Amplifier

 The JFET must be biased in the active region to use it as an amplifier. There are many biasing methods namely self bias(see how to bias JFET transistor), drain feedback bias, Voltage divider bias, Two Supply Bias and Two Supply Bias with Current Source

Here we will use voltage divider biasing method which is considered best for stability of the quiescent point. The JFET transistor used is the 2N5457 transistor. The following shows the chosen bias point(q-point) on the drain graph for 2N5457.

bias point hartley oscillator design

 The bias point is located at,

\(V_{DSQ}\) = 2.5V,  \(I_{DQ}\) = 473uA 

Also from the drain curve(or datasheet),

 \( V_{GS(off)}=-2.4V\) and \( I_{DSS}=1mA\)

The gate to source voltage required for this bias point drain current can be calculated using Shockley equation. Using Shockley equation,

\(I_D=I_{DSS} (1- \frac{V_{GS}}{V_{GS(off)}})^2\)

which can be resolved to,

\( V_{GS}= V_{GS(off)}(1- \sqrt{\frac{I_{DQ}}{I_{DSS}}})\)


 \( V_{GS}= -2.4V(1- \sqrt{\frac{473uA}{1mA}}) \)

that is we get,   \( V_{GS}\simeq -0.75V\)

Let the source voltage be,

\(V_S = 1V\)

Then the gate voltage is,

\(V_G = V_S+V_{GS} = 1V - 0.75V\)

that is, \(V_G = 0.25V\)

To get this gate voltage we use the voltage divider using the resistors R1 and R2.

We have,

\(V_G = \frac{R_2}{R_1+R_2}V_{DD}\)


\(R_2 = \frac{V_G}{V_{DD}-V_G}R_1\)

or, \(R_2 = \frac{V_G}{V_{DD}-V_G}R_1\)

Let \(R_1=10k\Omega\)

then, \(R_2 = \frac{0.25V}{5V-0.25V}10k\Omega\)

that is, \(R_2 \simeq 526\Omega\)

The source resistor can be calculated as follows.

\(R_S = \frac{V_S}{I_D}\) 

we have set earlier, \(V_S = 1V\)

therefore, \(R_S = \frac{1V}{473uA  }\) 

that is, \(R_S \simeq 2.11k \Omega\)

Finally, we can calculate the drain resistor as follows,

\(R_D = \frac{V_{DD}- V_D}{I_D}\) 

where, \(V_D=V_{DS}+V_S = 2.5V+1V=3.5V\)

or, \(R_D = \frac{5V-3.5V}{473uA}=\frac{1.5V}{0.473mA }\) 

that is, \(R_D \simeq 3.17k\Omega\)

Feedback Circuit

The inductor L1 and L2 along with capacitor C forms the feedback circuit. In Hartley oscillator, inductor divider circuit is used. The Hartley oscillator formula is,

\(f_r = \frac{1}{2 \pi \sqrt{L C}}\)

where, \(L=L1+L2\)

We can use the online Hartley oscillator frequency calculator to calculate inductor or capacitor value(s) for desired frequency. Suppose we want the frequency to be 11.25KHz then with 0.1uF capacitor the value of the two inductors will be 1mH.

All the above calculated resistor values and the coupling and bypass capacitor values can be calculated using the online JFET voltage divider biased amplifier calculator.


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